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Design of Cost-Efficient Interconnect Processing Units

Citation Information

Design of Cost-Efficient Interconnect Processing Units

Spidergon STNoC

Marcello Coppola , Miltos D. Grammatikakis , Giuseppe Maruccia , Riccardo Locatelli and Lorenzo Pieralisi

CRC Press 2008

Print ISBN: 978-1-4200-4471-3

eBook ISBN: 978-1-4200-4472-0

Table of Contents

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Title
I
Front Matter

Abstract - Hi-Res PDF (232 KB) - PDF w/links (233 KB)
1
Chapter 1. Towards Multicores

Abstract - Hi-Res PDF (614 KB) - PDF w/links (525 KB)
41
Chapter 2. On-Chip Bus vs. Network-on-Chip

Abstract - Hi-Res PDF (613 KB) - PDF w/links (578 KB)
69
Chapter 3. NoC Topology

Abstract - Hi-Res PDF (789 KB) - PDF w/links (779 KB)
103
Chapter 4. The Spidergon STNoC

Abstract - Hi-Res PDF (1624 KB) - PDF w/links (1711 KB)
169
Chapter 5. SoC and NoC Design Methodology and Tools

Abstract - Hi-Res PDF (1334 KB) - PDF w/links (1451 KB)
227
Chapter 6. Conclusions and Future Work

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235
References

Abstract - Hi-Res PDF (223 KB) - PDF w/links (254 KB)