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http://dx.doi.org/10.1201/9781420007954
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ContentsAbstract - Hi-Res PDF (489 KB) - PDF w/links (471 KB)
1-2
Chapter 1. Design FlowsDavid Hathaway, Leon Stok, David Chinnery, Kurt KeutzerAbstract - Hi-Res PDF (365 KB) - PDF w/links (366 KB)
2-1
Chapter 2. Logic SynthesisSunil P. Khatri, Narendra V. ShenoyAbstract - Hi-Res PDF (409 KB) - PDF w/links (411 KB)
3-1
Chapter 3. Power Analysis and Optimization from Circuit to Register-Transfer LevelsVivek Tiwari, Jose Monteiro, Rakesh PatelAbstract - Hi-Res PDF (421 KB) - PDF w/links (430 KB)
4-1
Chapter 4. Equivalence CheckingAndreas Kuehlmann, Fabio SomenziAbstract - Hi-Res PDF (521 KB) - PDF w/links (522 KB)
5-1
Chapter 5. Digital Layout — PlacementAndrew B. Kahng, Sherief RedaAbstract - Hi-Res PDF (442 KB) - PDF w/links (443 KB)
6-1
Chapter 6. Static Timing AnalysisSachin S. SapatnekarAbstract - Hi-Res PDF (538 KB) - PDF w/links (552 KB)
7-1
Chapter 7. Structured Digital DesignFan Mo, Robert K. BraytonAbstract - Hi-Res PDF (763 KB) - PDF w/links (773 KB)
8-1
Chapter 8. RoutingLouis SchefferAbstract - Hi-Res PDF (495 KB) - PDF w/links (505 KB)
9-1
Chapter 9. Exploring Challenges of Libraries for Electronic DesignJames Hogan, Scott T. BeckerAbstract - Hi-Res PDF (443 KB) - PDF w/links (446 KB)
10-1
Chapter 10. Design ClosureJohn M. Cohn, Peter J. OslerAbstract - Hi-Res PDF (7897 KB) - PDF w/links (952 KB)
11-1
Chapter 11. Tools for Chip-Package CodesignPaul D. FranzonAbstract - Hi-Res PDF (1489 KB) - PDF w/links (516 KB)
12-1
Chapter 12. Design DatabasesMark BalesAbstract - Hi-Res PDF (1321 KB) - PDF w/links (1323 KB)
13-1
Chapter 13. FPGA Synthesis and Physical DesignVaughn Betz, Mike HuttonAbstract - Hi-Res PDF (1652 KB) - PDF w/links (1654 KB)
14-2
Chapter 14. Simulation of Analog and RF Circuits and SystemsAlan Mantooth, Jaijeet RoychowdhuryAbstract - Hi-Res PDF (2090 KB) - PDF w/links (1786 KB)
15-1
Chapter 15. Simulation and Modeling for Analog and Mixed-Signal Integrated CircuitsGeorges G. E. Gielen, Joel R. PhillipsAbstract - Hi-Res PDF (9057 KB) - PDF w/links (2011 KB)
16-1
Chapter 16. Layout Tools for Analog Integrated Circuits and Mixed-Signal Systems-on-ChipRob A. Rutenbar, John M. CohnAbstract - Hi-Res PDF (3927 KB) - PDF w/links (759 KB)
17-1
Chapter 17. Design Rule CheckingLaurence Grodd, Robert Todd, Katherine FettyAbstract - Hi-Res PDF (3677 KB) - PDF w/links (1836 KB)
18-1
Chapter 18. Resolution Enhancement Techniques and Mask Data PreparationFranklin M. SchellenbergAbstract - Hi-Res PDF (6350 KB) - PDF w/links (1554 KB)
19-1
Chapter 19. Design for Manufacturability in the Nanometer EraCarlo Guardiani, Nicola Dragone, Andrzej J. StrojwasAbstract - Hi-Res PDF (2843 KB) - PDF w/links (1488 KB)
20-1
Chapter 20. Design and Analysis of Power Supply NetworksRajendran Panda, Rajat Chaudhry, David Blaauw, Sanjay PantAbstract - Hi-Res PDF (1774 KB) - PDF w/links (635 KB)
21-1
Chapter 21. Noise Considerations in Digital ICsVinod KariatAbstract - Hi-Res PDF (540 KB) - PDF w/links (548 KB)
22-1
Chapter 22. Layout ExtractionPeter Spink, Mark Basel, Chi-Yuan Lo, William Kao, Louis Scheffer, Raminderpal SinghAbstract - Hi-Res PDF (684 KB) - PDF w/links (705 KB)
23-1
Chapter 23. Mixed-Signal Noise Coupling in System-on-Chip DesignMakoto Nagata, Nishath VergheseAbstract - Hi-Res PDF (1507 KB) - PDF w/links (1520 KB)
24-1
Chapter 24. Process SimulationMark D. JohnsonAbstract - Hi-Res PDF (2447 KB) - PDF w/links (918 KB)
25-1
Chapter 25. Device Modeling —From Physics to Electrical Parameter ExtractionEdwin C. Kan, Chang-Hoon Choi, Robert W. DuttonAbstract - Hi-Res PDF (1942 KB) - PDF w/links (1943 KB)
26-1
Chapter 26. High-Accuracy Parasitic ExtractionRalph Iverson, Mattan KamonAbstract - Hi-Res PDF (1188 KB) - PDF w/links (1189 KB)
