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http://dx.doi.org/10.1201/9781420013481
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Front MatterAbstract - Hi-Res PDF (175 KB) - PDF w/links (175 KB)
Chapter 1. Introduction to Physical DesignDinesh P. MehtaAbstract - Hi-Res PDF (76 KB) - PDF w/links (77 KB)
Chapter 2. Layout SynthesisRalph H. J. M. OttenAbstract - Hi-Res PDF (503 KB) - PDF w/links (504 KB)
Chapter 3. Metrics Used in Physical DesignFrank LiuAbstract - Hi-Res PDF (432 KB) - PDF w/links (432 KB)
Chapter 4. Basic Data StructuresDinesh P. Mehta, Hai ZhouAbstract - Hi-Res PDF (353 KB) - PDF w/links (354 KB)
Chapter 5. Basic Algorithmic TechniquesVishal Khandelwal, Ankur SrivastavaAbstract - Hi-Res PDF (227 KB) - PDF w/links (228 KB)
Chapter 6. Optimization Techniques for Circuit Design ApplicationsZhi-Quan LuoAbstract - Hi-Res PDF (249 KB) - PDF w/links (250 KB)
Chapter 7. Partitioning and ClusteringDorothy KucarAbstract - Hi-Res PDF (555 KB) - PDF w/links (556 KB)
Chapter 8. FloorplanningSusmita Sur-KolayAbstract - Hi-Res PDF (431 KB) - PDF w/links (432 KB)
Chapter 9. Slicing FloorplansTing-Chi Wang, Martin D. F. WongAbstract - Hi-Res PDF (482 KB) - PDF w/links (483 KB)
Chapter 10. Floorplan RepresentationsEvangeline F. Y. YoungAbstract - Hi-Res PDF (433 KB) - PDF w/links (434 KB)
Chapter 11. Packing Floorplan RepresentationsTung-Chieh Chen, Yao-Wen ChangAbstract - Hi-Res PDF (1042 KB) - PDF w/links (1043 KB)
Chapter 12. Recent Advancesin FloorplanningDinesh P. Mehta, Yan FengAbstract - Hi-Res PDF (351 KB) - PDF w/links (352 KB)
Chapter 13. Industrial Floorplanning and PrototypingLouis K. SchefferAbstract - Hi-Res PDF (855 KB) - PDF w/links (331 KB)
Chapter 14. PlacementGi-Joon Nam, Paul G. VillarrubiaAbstract - Hi-Res PDF (938 KB) - PDF w/links (360 KB)
Chapter 15. Partitioning-Based MethodsJarrod A. Roy, Igor L. MarkovAbstract - Hi-Res PDF (1554 KB) - PDF w/links (844 KB)
Chapter 16. Placement Using Simulated AnnealingWilliam SwartzAbstract - Hi-Res PDF (407 KB) - PDF w/links (275 KB)
Chapter 17. Analytical Methods in PlacementUlrich Brenner, Jens VygenAbstract - Hi-Res PDF (2080 KB) - PDF w/links (646 KB)
Chapter 18. Force-Directed and Other Continuous Placement MethodsAndrew Kennings, Kristofer VorwerkAbstract - Hi-Res PDF (1450 KB) - PDF w/links (636 KB)
Chapter 19. Enhancing Placement with Multilevel TechniquesJason Cong, Joseph R. ShinnerlAbstract - Hi-Res PDF (450 KB) - PDF w/links (451 KB)
Chapter 20. Legalization and Detailed PlacementAmeya R. Agnihotri, Patrick H. MaddenAbstract - Hi-Res PDF (816 KB) - PDF w/links (581 KB)
Chapter 21. Timing-Driven PlacementDavid Z. Pan, Bill Halpin, Haoxing RenAbstract - Hi-Res PDF (300 KB) - PDF w/links (301 KB)
Chapter 22. Congestion-Driven Physical DesignSaurabh N. Adya, Xiaojian YangAbstract - Hi-Res PDF (545 KB) - PDF w/links (354 KB)
Chapter 23. Global Routing Formulation and Maze RoutingMuhammet Mustafa Ozdal, Martin D. F. WongAbstract - Hi-Res PDF (679 KB) - PDF w/links (470 KB)
Chapter 24. Minimum Steiner Tree Construction*Gabriel Robins, Alexander ZelikovskyAbstract - Hi-Res PDF (602 KB) - PDF w/links (371 KB)
Chapter 25. Timing-Driven Interconnect SynthesisJiang Hu, Gabriel Robins, Cliff C. N. SzeAbstract - Hi-Res PDF (531 KB) - PDF w/links (532 KB)
Chapter 26. Buffer Insertion BasicsJiang Hu, Zhuo Li, Shiyan HuAbstract - Hi-Res PDF (387 KB) - PDF w/links (387 KB)
Chapter 27. Generalized Buffer InsertionMiloš Hrkić, John LillisAbstract - Hi-Res PDF (247 KB) - PDF w/links (248 KB)
Chapter 28. Buffering in the Layout EnvironmentJiang Hu, C. N. SzeAbstract - Hi-Res PDF (422 KB) - PDF w/links (423 KB)
Chapter 29. Wire SizingSanghamitra Roy, Charlie Chung-Ping ChenAbstract - Hi-Res PDF (291 KB) - PDF w/links (292 KB)
Chapter 30. Estimation of Routing CongestionRupesh S. Shelar, Prashant SaxenaAbstract - Hi-Res PDF (288 KB) - PDF w/links (244 KB)
Chapter 31. Rip-Up and RerouteJeffrey S. SaloweAbstract - Hi-Res PDF (801 KB) - PDF w/links (801 KB)
Chapter 32. Optimization Techniquesin RoutingChristoph AlbrechtAbstract - Hi-Res PDF (295 KB) - PDF w/links (296 KB)
Chapter 33. Global Interconnect PlanningCheng-Kok Koh, Evangeline F. Y. Young, Yao-Wen ChangAbstract - Hi-Res PDF (1216 KB) - PDF w/links (644 KB)
Chapter 34. Coupling NoiseRajendran Panda, Vladimir Zolotov, Murat BecerAbstract - Hi-Res PDF (440 KB) - PDF w/links (441 KB)
Chapter 35. Modeling and Computational LithographyFranklin M. SchellenbergAbstract - Hi-Res PDF (3959 KB) - PDF w/links (1802 KB)
Chapter 36. CMP Fill SynthesisAndrew B. Kahng, Kambiz SamadiAbstract - Hi-Res PDF (792 KB) - PDF w/links (561 KB)
Chapter 37. Yield Analysis and OptimizationPuneet Gupta, Evanthia PapadopoulouAbstract - Hi-Res PDF (479 KB) - PDF w/links (309 KB)
Chapter 38. Manufacturability-Aware RoutingMinsik Cho, Joydeep Mitra, David Z. PanAbstract - Hi-Res PDF (940 KB) - PDF w/links (633 KB)
Chapter 39. Placement-Driven Synthesis Design Closure ToolNathaniel Hieter, Arjen Mets, Ruchir Puri, Lakshmi Reddy, Haoxing Ren, Louise TrevillyanAbstract - Hi-Res PDF (1189 KB) - PDF w/links (583 KB)
Chapter 40. X Architecture Place and RouteSteve Teig, Asmus Hetzel, Joseph Ganley, Jon Frankle, Aki FujimuraAbstract - Hi-Res PDF (1843 KB) - PDF w/links (938 KB)
Chapter 41. Inductance Effects in Global NetsYehea I. IsmailAbstract - Hi-Res PDF (493 KB) - PDF w/links (494 KB)
Chapter 42. Clock Network DesignChris Chu, Min PanAbstract - Hi-Res PDF (785 KB) - PDF w/links (786 KB)
Chapter 43. Practical Issues in Clock Network DesignChris Chu, Min PanAbstract - Hi-Res PDF (2035 KB) - PDF w/links (707 KB)
Chapter 44. Power Grid DesignHaihua Su, Sani NassifAbstract - Hi-Res PDF (446 KB) - PDF w/links (447 KB)
Chapter 45. Field-Programmable Gate Array ArchitecturesSteven J. E. Wilton, Nathalie Chan King Choy, Scott Y. L. Chin, Kara K. W. PoonAbstract - Hi-Res PDF (472 KB) - PDF w/links (473 KB)
Chapter 46. FPGA Technology Mapping, Placement, and RoutingKia BazarganAbstract - Hi-Res PDF (2304 KB) - PDF w/links (1604 KB)
Chapter 47. Physical Design for Three-Dimensional CircuitsKia BazarganAbstract - Hi-Res PDF (1133 KB) - PDF w/links (637 KB)